Imaging devices, including charge coupled devices (CCD) and complementary metal oxide semiconductor (CMOS) imagers, are commonly used in photo-imaging applications.
A CMOS imager circuit includes a focal plane array of pixels, each of the pixels including a photosensor, for example, a photogate, photoconductor or a photodiode for accumulating photo-generated charge a portion of the substrate. Each pixel has a charge storage region, formed on or in the substrate, which is connected to the gate of an output transistor that is part of a readout circuit. The charge storage region may be constructed as a floating diffusion region. In some imager circuits, each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state; (4) transfer of charge to the storage region; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
CMOS imagers of the type discussed above are generally known as discussed, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524 and U.S. Pat. No. 6,333,205, assigned to Micron Technology, Inc., which are hereby incorporated by reference in their entirety.
In CMOS and other imagers and in other lower power integrated circuit applications, it is common to have multiple power domains to fulfill power and performance requirements. A dual power supply strategy is often employed in output drivers. This dual power supply approach provides high output driving capability and a good interface with core logic.
FIG. 1 illustrates an output driver circuit 100, which may be used in integrated circuit applications, for example, within the peripheral logic circuit of a CMOS imager. The circuit 100 comprises a PMOS transistor P100, NMOS transistor N100 connected in series with transistor P100, reset switches S100, S102, capacitors CP and CN and resistors RP, RN. The input into the circuit 100 is at node A and the output from the circuit 100 is at node Z. As can been seen in FIG. 1, the circuit 100 employs an RC time constant circuit to control the rise and fall of the signals that activate the gates of the of the NMOS and PMOS transistors N100, P100. The NMOS transistor N100 rising output slew rate is determined by the values of resistor RN and capacitor CN which are connected across the input node A and the output node Z. The gate of transistor N100 is connected to the node between resistor RN and capacitor CN and to switch S102, which is also connected to ground GND. Similarly, the PMOS transistor P100 rising output slew rate is determined by the values of series connected resistor RP and capacitor CP likewise connected across the input node A and output node Z. The gate of transistor P100 is connected to the node between RP and capacitor CP and to switch S100, which is also connected to the power supply VDDIO. The output drive strength and the slew rate of either transistor P100, N100 ultimately depends on the variation of the power supply VDDIO voltage.
In order to make an output driver (e.g., driver circuit 100) applicable to a variety of applications, the IO power supply VDDIO of the output driver requires a wide operating range; that is, there may be a wide variation in the voltage level of power supply VDDIO. As a result, the output driver has a large variation in both drive strength and slew rate depending on the value of power supply VDDIO. In addition, higher supply voltages lead to poor simultaneous switching output (SSO) performance. This, in turn, typically requires thicker metal tracks and more power supply pads in order to compensate for the poor SSO performance. Accordingly, there is a need and a desire for an output driver that provides a more constant output drive and slew rate for a given load which in turn leads to better SSO performance.